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FPGA Verification Engineer

@Sii Sp. z o.o. SystemVerilog UVM SoC ARM CSS DDR4/DDR5 PCIe Gen5 Gen4 IP Synopsys VCS SpyGlass Verdi JasperGold Python TCL Perl Ethernet DPDK
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FPGA Design Engineer

@Sii Sp. z o.o. Verilog SystemVerilog SoC ARM CSS DDR4/DDR5 PCIe Gen5 Gen4 IP Design Compiler SpyGlass CDC/DFT Fusion Compiler Python TCL Linux firmware Linux